Your guess is almost correct. However this behavior has to be done also
in multi-core single processor systems.
Your processor can have multiple cores, therefore when writing a cache
line (in a WB cache), the core that issues the write needs to get exclusive
access to that line. If the line intended for write is marked as dirty it
will be "flushed" to the lower memories before being written with the new
In a multi-core CPU, each core has it's own L1 cache and there is the
possibility that each core could store a copy of a shared L2 line.
Therefore you need this behavior for Cache Coherency.
You should find out more by reading about MESI protocol and it's derivations.